If the GPL’d source code of the OpenSPARC chip design, Open Boot PROM, hypervisor and other architecture tools wasn’t good enough to make you drool, a company called Simple RISC has made a derived single core design which you can simulate and synthesize using Icarus Verilog and other supporting free software tools on Linux. A great day for freedom!
Simple RISC says in the simulation docs that Icarus Verilog is much slower than other commercial software for simulation. However, there are other free software alternatives like Verilator (which claims that it’s about 100 times faster than Icarus Verilog) that one can try using.
Sun: Not being your apologist, but I know you’ve been getting some bad press in the freedom industry 
lately. What you have done with OpenSPARC rocks. I hope you think and make a right choice for the proposed open source JDK license.
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